Conventionally in the communication of data, a data transmission apparatus may use a multiplexer to convert parallel signals into a serial signal for transmission to a receiving apparatus. For example, a technology is known in which multiple stages of multiplexers that convert 2 parallel signals into a serial signal according to the value of a clock signal are disposed such that multiplexers farther downstream have clock signals of higher frequencies, whereby staged multiplexing is performed (for example, refer to Japanese Laid-Open Patent Publication No. H11-17636).
A further technology is known in which a converter converts parallel signals into a serial signal (for example, refer to Japanese Laid-Open Patent Publication No. 2002-260908).
Nonetheless, if the frequency of the clock signal provided to a multiplexer is high, the operation of the multiplexer may become unstable.